In digital computer systems, a timing signal called the clock is used to provide timing reference for communication between functional units of the system. The abilities to start and stop the clock and to issue one clock pulse (single cycle) are required for the clock control logic. When errors are detected in the computer system, the clock is stopped, freezing the state of the system and preventing errors from propagating to the entire system. In most high speed, high performance computer systems, it usually takes several clock cycles to stop the clock after an error occurs. In prior art designs of the clock control circuitry, such as that of the Amdahl 5870 computer, the number of clock cycles it takes to stop the clock depends on whether the system clock is being single cycled or running at full speed. It takes fewer cycles to stop the clock in single cycle mode than in full speed mode. This makes debugging the computer complicated.
The clock signal is distributed to different units in the computer system through a clock distribution network. The propagation delay from the clock source to each subunit designed to be equal, so that each subunit receives the same clock pulse at the same time.
The total delay from the clock source to each subunit is the sum of all of the wiring delay and the propagation delay on the logic gates. Due to the physical layout of the computer system, the wiring propagation delay from the clock source to each unit may or may not be equal. Units whose physical location is closer to the clock source will have less wiring delay than units whose physical location is further away. The propagation delay and the wiring delays are adjusted using delay chains so that the total delay from the clock source to each subunit is the same.
In current systems, instead of using one delay chain for each unit, one main delay chain is used. Each unit taps its clock signal off the main delay chain at different places to equalize delays for all the clock signals. This implementation saves hardware, for some of the delay hardware can be shared among different units.
Clocks tapped off from the beginning of the delay chain are called "early" clocks. Similarly, a clock tapped off from the end of the delay chain is called a "late" clock and a clock tapped off from the middle of the delay chain is called a "normal" clock. Normal clocks are "late" with respect to early clocks. The timing of early, normal and late clocks is relative. The degree of earlyness and lateness is measured in seconds, nanoseconds, etc. A 5 nanoseconds early clock will be active 5 nanoseconds before the normal clock becomes active.
Two kinds of clock signals are mentioned in this application; the basic clock and the system clock.
The basic clock, typically generated from an oscillator, is used to provide timing reference for the clock control circuitry. The basic clock runs at all times and cannot be stopped by the clock control circuitry.
The system clock is used to provide timing references for units in the system other than the clock control. One important characteristic of the system clock which is different from the basic clock is that the system clock can be started and stopped, and one clock pulse can be issued (single cycle). When an error is detected in the computer system, the system clock is stopped to freeze the state of the machine so that error recovery can take place.
FIG. 1 shows the block diagram of a clock control circuit for an ideal case. The conventional way of obtaining system clock 13 is to use a state machine 11 to generate a clock enable signal 16, and then to combine the enable signal 16 with the basic clock signal 12 in AND gate 17. System clock 13 is delayed by delay lines 18, 19 and 20 to generate normal system clock 21, 10 ns early system clock 22, 20 ns early system clock 23, and 30 ns early system clock 24 to match the wiring delay from clock control to the computer system 15.
The console 10 shown in the figure is a service processor which runs off the basic clock 12. It monitors the activity of the main computer. The console runs diagnostic programs when errors occur in the main computer. If the error is recoverable, then error recovery takes place. Another function of the console is to provide interface between the computer and the operator. Operator commands can be issued to the main computer through the console. One set of commands which is crucial to error recovery and to the operator is the system clock control commands. The clock control commands are used to start, to stop, and to single cycle the system clocks.
The clock control state machine 11 and the console 10 run under basic clock 12. This is necessary, for if system clock 13 were used, when the system clock was stopped, there would be no clock signal to the console 10 and the state machine 11. The state machine 11 and the console 10, therefore, could not change state anymore.
There are other signals generated by the system that can stop the system clock 13. The clock pinch signal 14, for instance, indicates that errors have been detected in the system and the system clock needs to be stopped to prevent the error from propagating to the entire machine.
The timing relation of the enable 16 and the basic clock signal 12 is adjusted so that the enable signal always switches during the window of the basic clock signal 12 in which it is not active.
The generation of early and late clocks needs to be cycle time independent. When the cycle time of the oscillator generating the basic clock changes, the early and late relationship with respect to the normal clock should remain fixed. That is, a 5 nanoseconds early clock should always lead the normal clock by 5 nanoseconds, regardless of whether the cycle time is 15 nanoseconds or 50 nanoseconds. As mentioned before, enable signals used to stop and start system clocks are adjusted so that the enable signal does not switch when the basic clock signal is active. This implies that enable signals have the same timing as the basic clock signals with which they are ANDed. Therefore, an early enable signal whose timing is sufficiently early to match the earliest basic clock is needed. Enable signals of other timing can be generated by delaying this early enable signal. One method of achieving the early enable is to employ a so-called early-up chain.
FIG. 2 and FIG. 3 show a block diagram and clock signal timing diagram, respectively, of the early-up chain 20. The early-up chain 20 is a set of latches 21, 22, 23, 24 connected in a chain. Each latch runs on a different timing clock. The normal clock 25 latches the head latch 21 of the chain. The clocks get earlier and earlier until the end of the chain, where the clock 26 is the earliest. A normal signal going through this chain will be synchronized with an early clock signal. This early clock synchronized signal is then incrementally delayed to provide signals synchronized with later clocks. For example, assume the cycle time is 15 nanoseconds and the clocks to the early-up chain are 10 nanoseconds early at latch 22, 20 nanoseconds early at latch 23, and 30 nanoseconds early at latch 24. It can be seen in FIG. 3 that a signal asserted at cycle one 30 of the normal clock will be latched in cycle two 31 of the 10 nanoseconds early clock, and its output will be in turn latched in cycle three 32 of the 20 nanoseconds early clock. Finally, the signal will be latched in cycle four 32 of the 30 nanoseconds early latch. The output of latch 24 is synchronized with cycle four of the 30 nanoseconds early clock. It can then be incrementally delayed to provide signals synchronized with later clocks. It takes four clock cycles for a normal signal to go through the four latch early-up chain including the delay. If the cycle time changes, the result is the same; it still takes four clock cycles for a normal signal to go through the early-up chain plus equalizing delay. The cycle time and the timing of the clocks mentioned the previous example are for convenience of calculation. Other numbers may be used as long as the timing difference between one clock and the next earlier clock plus logic delay from one latch to the next latch is less than the total cycle time.
A typical implementation of a prior art system clock control circuit 40 is seen in FIG. 4. The console 41 issues system clock control commands to start, stop and single cycle the system clocks. The basic clock signal 42 from an oscillator (not shown) is incrementally delayed 43 to generate normal 44, and three different early clocks 45, 46, 47. The system clock control state machine 48 and the early-up chain 49 run under basic clocks. After going through the early-up chain 49, normal enable signal 50 generated by the state machine 48 becomes early enable signal 51. The early enable signal 51 is then incrementally delayed 52 to generate enable signals 53 with the correct timing with respect to the basic clock signals 44, 45, 46, 47 from which system clocks 54 are formed through AND gates 55.
In this embodiment, only one early-up chain running off the basic clock is used for the enable signal. When the system clock pinch signal is not active, the system clock stops and starts on the same cycle boundary regardless of the cycle time of the basic clock.
However, a problem arises when the clock pinch signal is active and the system clock is being single cycled. When in single cycle mode, the basic clocks to the state machine and the early-up chain are all running at speed. The only clock being single cycled is the system clock. Since the basic clock to the early-up chain is running, the enable signal will be able to go through the early-up chain to stop the system clock. It takes five basic clock cycles to stop the system clock (one cycle for state machine, four cycles for the early-up chain). However, it takes an indeterminate number of system cycles, because in single cycle the number of system and basic clock pulses do not match. When the number of system cycles between the time of a system error and the time that the system clock is stopped depends on circumstances at the time of the error, analysis of the state of the system as of the time of the error is difficult.